I. Field of the Disclosure
The technology of the disclosure relates generally to data buffers, and particularly to buffering time of such data buffers.
II. Background
Integrated circuits (ICs) designed with digital logic include multiple logic paths through which data may be transmitted. Each logic path has a corresponding delay, such that data transmitted through a particular logic path is received at an intended destination following the delay. The total delay corresponding to a particular logic path may include at least two types of delay, resistor-capacitor (RC) delay and gate delay. RC delay is attributable to the resistive and capacitive properties of metal components within the logic path, such as the wire on which the data is transmitted. Notably, the RC delay of a logic path remains constant across multiple voltage levels of transmitted data, because the resistive and capacitive properties of the logic path do not change with variations in voltage. Additionally, gate delay of a logic path is based on the number of logic gates within a logic path, as well as the switching speed of each logic gate. Thus, a gate delay of a logic path may increase if the logic gates switch more slowly due to a lower input voltage, and may decrease if the logic gates switch more quickly due to a higher input voltage.
Notably, each logic path within an IC may have an associated timing target that is affected by the delay of the logic path. For example, the delay of a logic path may cause data to arrive at a destination too early in time, thus generating logic errors in the IC. The timing of a logic path may be altered to help the logic path and IC achieve the associated timing targets so as to avoid logic errors. One way to alter the timing of a logic path is by inserting buffers into the logic path such that the buffers provide additional delay. For example, if a logic path has a race condition that causes data to arrive at a destination a certain number of clock cycles too early, one or more buffers may be inserted into the logic path such that the data is provided to the destination at the desired time.
Although inserting buffers into a logic path may allow the logic path to achieve timing targets when the provided data has a particular voltage, the logic path may fail to achieve timing targets when providing the data at other voltages. For example, the delay of a logic path at a higher voltage may be primarily attributable to RC delay. This is true because the higher voltage causes logic gates within the logic path to switch more quickly, thus reducing the gate delay associated with the logic path. Alternatively, the delay of a logic path at a lower voltage may be primarily attributable to gate delay. This is true because the lower voltage causes the logic gates within the logic path to switch more slowly, thus increasing the gate delay associated with the logic path. Thus, because the delay of a logic path may vary across higher and lower voltages, inserting buffers to achieve timing targets at one voltage may not achieve timing targets at another voltage. Therefore, it would be advantageous to employ buffers that could be used to achieve timing targets of logic paths in an IC across multiple voltage levels.